(a) Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device capable of being tested with a correct test mode.
(b) Description of the Related Art
DRAM (dynamic random access memory) increases its storage capacity four fold with each new generation. Then, it follows that if the number of I/O (input/output) units remains unchanged, the time length required to access all the memory cells in the memory device also increases by factor of four at each generation change. To avoid the delay for the access time, a x16 product is developed and commercially available which has 16 I/O pins to be accessed at one time for read/write operation compared to four I/O pins in the conventional x4 products. This permits the access time for all the memory cells to be unchanged between the x4 products and the x16 products. This also allows a screening test time for the memory products to be substantially reduced by a quadrature factor for x16 products than for x4 products having the same storage capacity.
However, in consideration that the memory tester generally has a number of read-out comparators depending on the number of products which can be simultaneously tested, if a x16 product tester contains the same number of comparators as for a x4 product tester, it follows that the number of memory devices which can be tested simultaneously is reduced by a factor of four for the x16 products than for the x4 products, thereby degrading the efficiency in the product screening test.
A bit-compressed test mode is recently proposed which prevents such degradation in the screening test by using a single I/O pin in read-write operation of data for four I/O pins among sixteen I/O pins, for example. An example of conventional circuit arrangements of semiconductor memory device operating in such a bit-compressed test mode is shown in FIG. 1.
In FIG. 1, it is to be noted that the arrangement of data-in buffers DIB1-DIB4 and data-out buffers DOB1-DOB4 which are associated with I/O pins IO1-IO4 have different configurations: the arrangement of data-in buffer DIB2 and data-out buffer DOB2 for IO2 pin is different from the arrangement for the remainder of data-in buffers DIB1, DIB3 and DIB4 and data-out buffer DOB1, DOB3 and DOB4, respectively, for I/O pins IO1, IO3 and IO4. In addition, NAND gates NA901-NA903 are provided for four banks of memory cells in the memory device to provide test result signal TFAILB through IO2 pin.
FIGS. 2 to 5 show circuit configurations of data-out buffers DOB1, DOB3 and DOB4, data-out buffer DOB2, data-in buffers DIB1, DIB3 and DIB4, and data-in buffer DIB2, respectively. In these drawings, as in the rest of the drawings, characters INV, NA, QN, QP, TG, NO and N attached to numerals show that those elements are inverter, NAND gate, N-ch MOSFET, P-ch MOSFET, transfer gate, NOR gate and signal node, respectively.
Referring to FIG. 2, each of data-out buffers DOB1, DOB3 and DOB4 has an inverter INV201 receiving TEST signal for effecting a bit-compressed test mode, a NAND gate NA201 receiving an output from INV201, data from bus RWBSTi (I=1,3 or 4) and output-enable signal OE, a NAND gate NA202 receiving an output from INV201, data from bus RWBSNi (1=1, 3 or 4) and output enable signal OE, inverters INV202 and INV203 receiving outputs from NA201 and NA202, respectively, and a pair of serial N-ch MOSFETs QN201 and QN202 receiving outputs from INV202 and INV203, respectively, at respective gates thereof, for supplying output signal to IOi pin (I=1, 3 or 4) through the node connecting the MOSFETs QN201 and QN202.
Referring to FIG. 3, data-out buffer DOB2 in FIG. 1 is similar to data-out buffers DOB1, DOB3 and DOB4 shown in FIG. 2 except that a test result signal TFAILB showing the occurrence of a failure in the read out data is used instead of TEST signal, and data from bus pair RWBST2 and RWBSN2 are used instead of data from bus pair RWBSTi and RWBSNi (I=1, 3 or 4), respectively.
Referring to FIGS. 4 and 5, data from Ioi pin (i=1 to 4) is supplied to respective data bus pairs RWBSTi/RWBSNi, as will be detailed below.
FIG. 6 shows a timing chart during a bit-compressed test mode in the memory device of FIG. 1. To enter a bit-compressed test mode from a mode, other than a test mode, which enables a normal write/read operation, a WCBR (WEB CASB Before RASB) cycle, which was standardized from 4 Mbit DRAMs, is effected while simultaneously supplying a predetermined specific key input to address key-input pins (A3, A4 and A5 pins in FIG. 1). At this time, no super-voltage (for example, 10 volts) which exceeds a normal voltage of 5 volts is applied to SVT (super-voltage pin, A0 in FIG. 1).
FIG. 6 illustrates write/read cycles during the bit-compressed test mode. Initially, RASB (row address strobe) is made low to accept a row address, and then CASB (column address strobe) is made low to accept a column address. WEB (write enable) is also made low, allowing W0 signal to turn from low to high to provide a single shot of W0 signal, whereby the first stage of IOi (where i=1 to 4) is enabled to accept write-in data or data to be written.
In the bit-compressed test mode, four I/O pins IO1 to IO4 are delegated by a single I/O pin (IO2, in this example) to achieve a bit-compressed test mode. Accordingly, it is only necessary that IO2 pin accepts data to be written, and it does not matter if other IOi pins (where i=1, 3 and 4) stay at a high impedance state (Hi-Z).
Referring to FIG. 4 which shows the circuit arrangement of data-in buffers DIB1, DBI3 and DIB4, even if W0 turns high to enable NAND gate NA403 to pass data from Ioi pin, transfer gate TG402 remains off because TEST signal remains high (and therefore an output from NOR gate N0401 is low ). Thus, written-in data which is fed from IOi pin (where i=1, 3 or 4) is not accepted. Instead, The inverted signal of data DIN2N, which is accepted by transfer gate 501 in data-in buffer DIB2 shown in FIG. 5 associated with IO2 pin, is fed through transfer gate TG401 in data-in buffer DIBi in FIG. 4 which is turned on by TEST signal.
Subsequently, W1 signal turns from low to high, whereby transfer gate TG501 (see FIG. 5) in data-in buffer DIB2 is turned off, allowing the accepted data to be latched by a flipflop formed by inverters INV504 and INV505. Thereafter, W2 signal turns from low to high, whereupon read/write bus pairs RWBSNi/RWBSTi for data-in buffer DIBi (where i=1, 3 and 4) shown in FIG. 4 and read/write bus pair RWBSN2/RWBST2 for data-in buffer DIB2 in FIG. 5 are driven in accordance with the same write-in data fed from IO2 pin. Accordingly, write amplifiers 105 shown in FIG. 1 drives data line pairs IOTi/IONi (where i=1, 2, 3 and 4) for writing the same data into respective memory cells in the four banks.
Now, the read cycle of the bit-compressed test mode will be described. As in the write cycle, RASB assumes low and then CASB assumes low to allow read-out addresses to be accepted. Data stored in memory cells at these addresses for four I/O pins are read out onto data line pairs IONi/IOTi (where i=1, 2, 3 and 4), whereby data amplifiers 104 drive respective bus pairs RWBSNi/RWBSTi (where i=1, 2, 3 and 4).
During the bit-compressed test mode of this example, a read/write operation occurs with the same data for four I/O pins, and hence data read out onto bus pairs RWBSTi/RWBSNi (where i=1, 2, 3 and 4) are equal to each other.
In FIG. 1, when data, all of which are equal to each other, are read out, either output from NAND gate NA901 or NA902 is low independently of whether the data read out are equal to 0 or 1, and hence the test result signal TFAILB from NAND gate NA903 remains high. In this case, it is known from the high level of TFAILB signal that equal data is read out for four IO pins. Referring to FIG. 3 which shows the circuit arrangement of data-out buffer DOB2 associated with pin IO2, data on bus pair RWBST2/RWBSN2 delegates the four data, and if output enable OEB is low and signal OE which is a complimentary signal of OEB is high, read-out data is delivered to IO2 pin. Specifically, in FIG. 3, when TFAILB signal assumes high and OE signal assumes high, NAND gate NA1001/NA1002 delivers an inverted signal of the complimentary signal from bus pair RWBST2/RWBSN2, which is again inverted in an inverter INV1001/INV1002 to feed N-ch transistor QN1001/QN1002, thereby delivering a voltage equivalent to the logic value of RWBST2 from IO2 pin.
In the data-out buffer DOBi for the remaining IOi (where I=1, 3 or 4) shown in FIG. 2, because TEST signal is high, an output from NAND gate NA201/NA202 which receives TEST and OE signals and data from corresponding bus pair RWBSTi/RWBSNi assumes a high level even if the signal OE is high. Accordingly, an output from inverter INV202/INV203 assumes a low level. In this state, N-ch transistors QN201 and QN202 are both turned off, and an output at IOi pin (i=1, 3 or 4) remains at its high impedance state(Hi-Z).
On the other hand, if one of data read out from bus pairs RWBSTi/RWBSNi (where i=1 to 4) is different from other data, TFAILB signal assumes low. Thus, as understood from FIG. 3, an output from NAND gate NA1001/NA1002 which receives TEST and OE signals and data from RWBST2/RWBSN2 assumes a high level, and N-ch transistors QN1001 and QN1002 are both turned off, resulting in an output of Hi-Z through IO2 pin, indicating the occurrence of a failure.
In the event that although the outputs for all the I/O pins (IO1 to IO4) are equal, and yet the data itself is wrong, a failure is detected by the fact that data delivered from IO2 pin is different from an expected value.
In the manner as described above, a read/write operation of data for four I/O pins IO1 to IO4 which are compressed into a single I/O pin is performed.
In the conventional semiconductor memory device described above, it is generally considered sufficient that attention be paid only to IO2 pin during the bit-compressed test mode. However, if the screening test is effected by paying attention only to IO2 pin, a product or products maybe erroneously determined as acceptable in the event that they pass a test effected for IO2 pin even if the product or products to be screened are involved with some defect in the memory device or other reason which prevents them from entering the bit-compressed test mode. Thus, a problem occurs that bank for the IO1, IO3 and IO4 pins may not be properly tested.